1. Field of the Invention
Embodiments of the present invention relate to a semiconductor die substrate panel including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated contacts.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate. The substrate may in general include a rigid, dielectric base having a conductance pattern, generally of copper or copper alloy, etched on respective sides. Electrical connections are formed between the die and the conductance pattern(s), and the conductance patterns(s) provide an electric lead structure for communication between the die and an external electronic system. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to form a protected semiconductor package.
While the copper conductance patterns may be etched to high precision, the poor corrosion properties of copper make it undesirable for certain applications. In the presence of moisture, air and chlorine, bare copper is readily tarnished, making it unsuitable for subsequent soldering and die attach operations. Similarly, certain packages, such as land grid array (LGA) and ball grid array (BGA) packages include contact fingers formed on a lower surface of the package and exposed outside of the package for establishing electrical connection between the package and an external electronic device. If the contact fingers were formed of bare copper, tarnishing and corrosion would damage the fingers over time.
It is therefore known to plate copper leads at their solder or through-hole points, and at the contact fingers. Various plating processes are known for applying a thin film of resistive material, such as tin, tin-lead, nickel, gold and nickel-gold. In one such process, a resistive material such as gold may be selectively plated onto the conductance pattern in an electroplating process. Referring to prior art FIG. 1, an electroplating process may result in a plurality of gold plating tails 20 on a substrate 22. The plating tails 20 may terminate at solder pads 24, through-holes 26, and contact fingers 28 provided for external electrical communication. Not all of the plating tails 20, pads 24 and fingers 28 are numbered in FIG. 1. Plating tails 20 and solder pads 24 shown in dashed lines in FIG. 1 are located on the underside of substrate 22. The substrate 22 further includes plating bars 30 for shorting together the various tails 20, pads 24, through-holes 26 and fingers 28 during the electroplating process.
In performing the electroplating process, the substrate 22 is immersed in a plating bath including metal ions in an aqueous solution. A current is supplied to the plating bars 30, which current travels through the plating tails 20, pads 24, through-holes 26 and fingers 28. When the current is delivered, the tails 20, pads 24, through-holes 26 and fingers 28 are electrified and a charge is created at their surface. The metal ions are attracted to the electrified and charged metal areas. In this way, a layer of gold or other plating metal of a desired thickness may be deposited.
After electroplating, the plating bar 30 is removed. It is important that the entire plating bar 30 is removed. However, owing to engineering tolerances, the blade, router or other device cutting the substrate and removing the plating bar may shift up, down, left and/or right off of the desired cutting line. Engineering tolerances of for example 50 microns (μm) are common. When removing the plating bar, if for example a sliver or portion of the plating bar is left due to a shift of the cutting device, as shown in prior art FIG. 2, this may result in certain tails being shorted together, such as for example tails 20a, 20b and 20c, and a malfunctioning of the integrated circuit formed thereby.
In order to prevent this, a cutting blade, router or other device 32 used to remove the plating bar is provided with a large width, w, as shown in prior art FIG. 3. Ideally, the width of the removal device 32 would be no larger than the width of the plating bar, which may for example be approximately 3 to 5 mils. However, engineering tolerances require that the blade be made wider to ensure that, if the removal device 32 shifts up/down or left/right while removing the plating bar, the entire plating bar is still removed. For example, if the removal device (shown in dashed lines in FIG. 3) varies a distance, Δ, from a desired removal path, the removal device must still have a width large enough to completely remove the plating bar.
As a result of the large width of the removal device required, as well as the space required on either side of the plating bar for engineering tolerances in the removal process, a relatively large kerf width, k (FIGS. 1 and 3), must be provided around each plating bar. Conventional kerf widths may be approximately 250 μm or larger. This large kerf width takes up space on substrate 22 which could otherwise be used for the circuit portion of the substrate.
It is known to also plate substrates in an electroless plating process which does not employ plating bars. In electroless plating, metal ions in an aqueous solution are deposited on a conductance pattern by a chemical reducing agent in solution instead of an electric charge. However, such electroless processes suffer from disadvantages including high expense and an inability to achieve precise patterning on the substrate.